In conventional photolithographic processing, integrated circuits are created on a semiconductor wafer by exposing the wafer with a pattern of features printed on a mask or reticle. The pattern of features selectively exposes photosensitive chemicals on the wafer that is then further chemically and mechanically processed to build up layers of the integrated circuit.
As the features on a mask become smaller and smaller, optical distortions can occur whereby the exposure pattern on a wafer will not match the pattern of features on the mask. To correct this, numerous resolution enhancement techniques such as the addition of subresolution assist features, phase shift masks, and optical and process correction (OPC) may be employed to improve the image fidelity so that the pattern imaged on a wafer more faithfully matches the corresponding pattern of features on the mask.
In OPC, estimates are made where the edges of a mask feature will be printed on a wafer. The expected printing location is then compared with a desired location and an edge placement error (EPE) is determined. From the EPE, a determination is made if the corresponding position of an edge on the photolithographic mask should be moved in order to precompensate for the expected error on the wafer.
FIG. 1 illustrates a simplified target feature 10 of a layout design that will create a corresponding object on a semiconductor wafer. The feature 10 is typically defined as a polygon in standard layout database language such as GDS-II or OASIS™. In order to simulate how the feature will be created on a wafer, the feature 10 is analyzed by a computer program that divides the perimeter of the feature with a number of fragmentation endpoints 12. The fragmentation endpoints 12 define corresponding edge segments 14, 16, 18, etc., that represent a portion of the perimeter of the polygon that defines the feature 10. Simulation sites 20 are then defined for one or more of the edge segments. A simulation site 20 defines a number of points where image intensity values or other process parameters are calculated. From the calculated image intensities at a simulation site, an EPE for a corresponding edge segment is calculated. From the EPE, an OPC software tool determines whether one or more edge segments in the layout should be moved in order to improve the printing fidelity on the wafer. After moving one or more of the edge segments, the EPEs may be recalculated and other adjustments made in an iterative fashion. Once all EPEs are within an acceptable tolerance, the corrected pattern of features is printed on a photolithographic mask for use in creating corresponding integrated circuits.
FIG. 2A illustrates a more realistic example of a layout design pattern and corresponding pattern of simulation sites. A pattern of design features 30 are fragmented into edge segments and assigned corresponding simulation sites 32 at which process parameters for a corresponding edge segment are calculated. In the example shown in FIG. 2A, the space between individual simulation sites is relatively large with respect to the area occupied by the layout features. However, FIG. 2B illustrates the same layout of design features 40 shown in FIG. 2A except the features are half the size. If features 40 are exposed with the same wavelength of light as the features in FIG. 2A, the size of the simulation sites should remain generally the same. As can be seen, the pattern of simulation sites 42 requires that many simulations be performed in very nearly the same location in the layout. The simulations may overlap in some areas but be absent in other areas, thereby resulting in an inefficient and time consuming process of estimating how the features will print.
Given these problems, there is a method of simplifying the estimation of process conditions in order to calculate optical and process corrections or other resolution enhancements for small features.